View PM8834QTR_4244932.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PM8834
4 A dual low side MOSFET driver
Features

Dual independent low side MOSFET driver with 4 A sink and source capability Independent enable for each driver Driver output parallel ability to support higher driving capability Matched propagation delays CMOS/TTL compatible input levels Wide input supply voltage range: 5 V to 18 V Embedded driver anti-shoot-through protection Low bias switching current Short propagation delays Wide operative temperature range: -40 C to 105 C S08 and VFDFPN8 3x3 mm package
SO8
VFDFPN8
Description
PM8834 is a flexible, high-frequency dual lowside driver specifically designed to work with high capacitive MOSFETs and IGBTs. Both PM8834 outputs can sink and source 4 A independently. Higher driving current can be obtained by putting in parallel the two PWM output. PM8834 provides two enable pins which can be used to enable the operation of one or both of the output lines. PM8834 works with CMOS/TTL compatible PWM signal. The driver is available in SO8 (PM8834) and VFDFPN8 3x3 mm (PM8834Q) packages.
Applications

Switch mode power supplies DC/DC converters Motor controllers Line drivers Class D switching amplifiers
Table 1.
Device summary
Temp range, C Package SO8 Packing Tube Tape and reel -40 - 105 PM8834Q VFDFPN8 Tube Tape and reel
Order codes PM8834 PM8834TR
PM8834QTR
October 2008
Rev 1
1/18
www.st.com 1
Contents
PM8834Q
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1 4.1.2 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Enable pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 4.3 4.4
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Parallel output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gate driver voltage flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 5.2 5.3 Output series resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
PM8834
Typical application circuit and block diagram
1
1.1
Typical application circuit and block diagram
Block diagram
Figure 1. Block diagram
3/18
Pin description and connection diagram
PM8834
2
Pin description and connection diagram
Figure 2. Pins connection (top view)
2.1
Pin description
Table 2.
Pin #
Pin descriptions
Name Function Enable input for Driver 1. Pull low to disable Driver1 (OUT1 will be low, PWM1 will be ignored). Even though internally pulled up to 3.3 V by 10 A current it is recommended to pull high up to VCC to enable the section. The pin features TTL/CMOS compatible thresholds. PWM input signal for driver 1 featuring TTL/CMOS compatible threshold and hysteresis. It is internally pulled down to GND with a 10 A current generator. All internal references, logic and drivers are referenced to this pin. Connect to the PCB ground plane. PWM input signal for driver 2 featuring TTL/CMOS compatible threshold and hysteresis. It is internally pulled down to GND with a 10 A current generator. Driver2 output. The output stage is capable of providing up to 4A drive current to the gate of a power MOSFET. IGBT are supported as well. A small series resistor can be useful to reduce dissipated power. PM8834 supply voltage. Bypass with low-ESR MLCC capacitor to GND. Driver1 output. The output stage is capable of providing up to 4A drive current to the gate of a power MOSFET. IGBT are supported as well. A small series resistor can be useful to reduce dissipated power. Enable input for Driver2. Pull low to disable Driver2 (OUT2 will be low, PWM2 will be ignored). Even though internally pulled up to 3.3 V by 10 A current it is recommended to pull high up to VCC to enable the section. The pin features TTL/CMOS compatible thresholds.
1
ENABLE_1
2
PWM_1
3
GND
4
PWM_2
5 6 7
OUT_2 VCC OUT_1
8
ENABLE_2
4/18
PM8834
Electrical specifications
2.2
Thermal data
Table 3.
Symbol
Thermal data
Value Parameter SO8 DFN8 45 5 150 -40 to 150 -40 to 150 -40 to 105 1.4 2.25 C/W C/W C C C C W Thermal resistance junction to ambient (Device soldered on 2s2p PC board - 67 mm x 67 mm) Thermal resistance junction to case Maximum junction temperature Storage temperature range Junction temperature range Operating ambient temperature range Maximum power dissipation at 25 C (Device soldered on 2s2p PC board) Unit
RthJA RthJC TMAX TSTG TJ TA PTOT
85 -
3
3.1
Electrical specifications
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol All pins IOUTx VHBM to GND DC output current ESD capability, human body model Parameter Value -0.3 to 19 500 2 Unit V mA kV
5/18
Electrical specifications
PM8834
3.2
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VCC = 5 V to 18 V, TJ = -40 C to 105 C unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-on ICC UVLOVCC VCC supply current VCC turn-ON VCC turn-OFF OUT_1, OUT_2 = OPEN VCC = 10 V; TJ = 25 C VCC rising VCC falling 3.6 4.5 4.4 3.8 4.6 mA V V
Input threshold PWM_x, ENABLE_x Input high - VIH Input low - VIL Rising threshold Falling threshold 0.8 2.2 1.1 2.5 V V
Drivers (OUT_1, OUT_2) VCC = 10 V; IOUT = 100 mA; TJ = 25 C VCC = 10 V; IOUT100mA; full temp. range Source current (1) Sink current (1) VCC = 10 V; COUT to GND = 10 nF VCC = 10 V; COUT to GND = 10 nF VCC = 10 V; IOUT = 100mA;TJ = 25 C VCC = 10 V; IOUT = 100 mA; full temp. range 4 5 0.7 1 1.3 1 1.3 1.5 A A
RDSON_H
Source resistance
ISOURCE ISINK
RDSON_L
Sink resistance
Switching time (PWM_1,PWM_2) tR Rise time VCC = 10 V; COUT to GND = 2.5 nF VCC = 10 V; COUT to GND = 14 nF Fall time VCC = 10 V; COUT to GND = 2.5 nF VCC = 10 V; COUT to GND = 14 nF 10 45 10 35 20 75 20 75 ns ns ns ns
tF
Propagation delay tD_LH tD_HL Delay - low to high Delay - high to low Matching between propagation delays
1. Parameter guaranteed by designed, not fully tested in production
COUT to GND = 2.5 nF COUT to GND = 2.5 nF
25 30 -5
35 40
45 50 5
ns ns ns
6/18
PM8834
Device description and operation
4
Device description and operation
PM8834 is a dual low side driver suitable for charging and discharging large capacitive loads like MOSFETs or IGBTs used in power supplies and DC/DC modules. PM8834 can sink and source 4 A on both low side driver branch but higher driving current can be obtained by paralleling its outputs. Even though this device has been designed to cope with loads requiring high peak current and fast switching time, the ultimate driving capability depends on the power dissipation in the device which must be kept below the power dissipation capability of the package. This aspect will be discussed in Section 5.2. For enhanced control of operation PM8834 make provision of dual independent active high enable pins (ENABLE_1 and ENABLE_2). Connecting those pin to GND pin, will disable the corresponding low side driver. PM8834 uses the VCC pin for supply and GND pin for return. The dual low-side driver has been design to work with supply voltage in the range of 5 to 18 V. Before VCC overcome the UVLO threshold (UVLOVCC), PM8834 keeps firmly-OFF both lowside MOSFETs then, after the UVLO has crossed, the PWM input keeps the control of the driver operations provided that the corresponding enable pin is active. Both PWM_1 and PWM_2 are internally pulled down so if left floating the corresponding output pins are discharged. Input pins (PWM_1, PWM_2, ENABLE_1 and ENABLE_2) are CMOS/TTL compatible with capability to work also with voltages up to VCC.
4.1
4.1.1
Input stage
PWM inputs
The input of the PM8834 dual low side driver are compatible to CMOS/TTL levels with capability to be pulled up to VCC. The relation between the input pins (PWM_1, PWM_2) and the corresponding PWM output is depicted in Figure 3. In the worst case, input levels above 2.5 V are recognized as high voltage and value below 0.8 V are recognized as low logic value. Propagation delays for high-low (tD_HL) and low-high (tD_LH) and rise (tR) and fall (tR) times have been designed to ensure operation in fast switching environment. Matching between delays in the two branches of the PM8834 ensure symmetry in the operations and allows parallel output functionality. Each PWM input feature 10 A pulldown to default OFF the status of the external MOSFET / IGBT.
7/18
Device description and operation Figure 3. Timing diagram
PM8834
4.1.2
Enable pins
PM8834 features two independent enable signals, namely ENABLE_1 and ENABLE_2, to control the operation of each low side driver. Both enable pins are internally pulled up to an internal 3.3 V reference and are active high. In noisy application where ENABLE_1 and ENABLE_2 are not in use, It is strongly recommended to connect these pins to VCC directly or with a pull-up resistor. ENABLE_1 and ENABLE_2 are compatible to CMOS/TTL levels and can be directly pulled up to VCC. By default, because of the internal pull-up, both drivers are enabled. It is possible to disable one or both low side drivers connecting the corresponding enable signal to GND.
4.2
Output stage
The output stage of the PM8834 make use of ST proprietary lateral DMOS as depicted in Figure 1. Both N-DMOS and P-DMOS have been sized to exhibit high driving peak current as well as low ON-resistance: typical peak current is 4 A while output resistances are 1 and 0.7 for P-DMOS and N-DMOS resistance respectively. The device features adaptive anti cross-conduction protection. PM8834 continuously monitors the status of the internal N-DMOS and P-DMOS: in case of a PWM transition, before switching on the desired DMOS, the device waits until the other DMOS is completely turned-off. No static current will then flow from VCC to GND.
8/18
PM8834
Device description and operation
4.3
Parallel output operation
For applications demanding high driving current capability (in excess of the 4 A provided by the single section), PM8834 allows paralleling the operation of the two drivers in order to reach higher current, up to 8 A. This configuration is depicted in Figure 4 where both PWM_1 and PWM_2 and OUT_1 and OUT_2 are tied together. The matching of internal propagation delays guarantee that the two drivers are switched on and off simultaneously. Figure 4. Single high current (up to 8 A) low-side driver configuration
4.4
Gate driver voltage flexibility
PM8834 allows the user to freely-select the gate drive voltage in order to optimize the efficiency of the application. The low-side MOSFET driving voltage depends on the voltage applied to VCC and can range between 5 V to 18 V.
9/18
Design guidelines
PM8834
5
5.1
Design guidelines
Output series resistance
An output resistance is generally introduced to allow high frequency operation without exceeding the maximum power dissipation of the driver package. The value of the output resistance can be obtained as described in Section 5.2 For application with supply voltages (VCC) greater than 15 V, with low capacitive loads (CG < 10 nF), caution must be taken when designing with PM8834. In these circumstances, due to its high peak current capability, severe undervoltage on the output pins may occur, which, if not limited in some way, can violate the safe operating area of the output stage of the device.To avoid this phenomena it is mandatory to add a gate resistor RG of at least 1 . Figure 5. is a synthetic view of the boundaries for safe operations of PM8834.
Figure 5.
Output series resistance
10/18
PM8834
Design guidelines
5.2
Power dissipation
PM8834 embeds two high current low side drivers that can be used to drive high capacitive MOSFETs. This section estimates the power dissipated inside the device in normal applications. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Bias power (PDC) depends on the static consumption of the device through the supply pins and it is simply obtained as follow:
P DC = V CC I CC
Drivers' power is the power needed by the driver to continuously switch ON and OFF the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term has to be determined to calculate the device power dissipation. The total power dissipated by each section to switch an external mosfets with gate charge QG is:
P SW = F SW ( Q G V CC )
When designing an application based on PM8834 it is recommended to take into consideration the effect of external gate resistors on the power dissipated by the driver. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. Referring to Figure 6, classical mosfet driver can be represented by a push-pull output stage with two different mosfets: P-DMOS to drive the external gate high and N-DMOS to drive the external gate low (with their own RdsON: Rhi, Rlo). The external power mosfet can be represented in this case as a capacitance (CG) that stores the gate-charge (QG) required by the external power MOSFET to reach the driving voltage (VCC). This capacitance is charged and discharged at the driver switching frequency FSW. The total power Psw is dissipated among the resistive components distributed along the driving path. According to the external gate resistance and the power-MOSFET intrinsic gate resistance, the driver dissipates only a portion of Psw as follow (per section):
R lo R hi 1 2 P SW = -- C G ( V CC ) Fsw ----------------------------------------- + ----------------------------------------- R + R 2 hi Gate + R i R lo + R Gate + R i
The total power dissipated from the driver can then be determined as follow:
P = P DC + 2 P SW
11/18
Design guidelines Figure 6. Equivalent circuit for MOSFET drive
PM8834
Figure 7.
Power dissipation estimation Figure 8. (single channel) for capacitive load of 10 nF with no gate resistor
Power dissipation estimation (single channel) for capacitive load of 10 nF with 4.7 gate resistor
5.3
Layout guidelines
The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (also EMI and losses) power connections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. Traces between the driver and the MOSFETS should be short and wide to minimize the inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count needs to be minimized to reduce the related parasitic effect. Small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply are also important. Locate the bypass capacitor (VCC capacitors) close to the device with the shortest possible loop and use wide copper traces to minimize parasitic inductance. To improve heat dissipation, place copper area under the IC. This copper area may be connected with other layers (if available) through VIAs to improve the thermal conductivity.
12/18
PM8834
Design guidelines The combination of copper pad, copper plane and VIAs under the driver allows the device to reach its best thermal performances. Figure 9. Driver turn-on and turn-off paths
Figure 10. External components placement example for SO8 package
Figure 11. External components placement example for DFN package
13/18
Package mechanical data
PM8834
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
14/18
PM8834 Table 6.
REF.
A A1 A2 A3 b D D2 E E2 e L ddd 0.30 0.18 2.85 2.20 2.85 1.40 0.50 0.40 0.50 0.08 11.81 3.00 0.55
Package mechanical data VFDFPN8 mechanical data
DIMENSIONS mm MIN. TYP. MAX. MIN.
0.80 0.90 0.02 0.65 0.20 0.25 3.00 0.30 3.15 2.70 3.15 1.75 7.086 112.2 86.61 112.2 55.11 19.68 15.74 19.68 3.149 118.1 1.00 0.05 0.80 21.65 31.49
mils TYP.
35.43 0.787 25.59 7.874 9.842 118.1 11.81 124.0 106.3 124.0 68.89
MAX.
39.37 1.968 31.49
PACKAGE AND PACKING INFORMATION
Very thin Fine pitch Dual Flat Package no Lead
Weight: not available
VFDFPN8 (3x3)
15/18
Package mechanical data Table 7.
Dim. Min A 1.35 Typ Max 1.75 Min 0.053 Typ
PM8834
SO-8 mechanical data
mm. inch Max 0.069
A1 A2 B C
D (1)
0.10 1.10 0.33 0.19 4.80 3.80 1.27 5.80 0.25 0.40 5
0.25 1.65 0.51 0.25 .00 4.00
0.004 0.043 0.013 0.007 0.189 0.15 0.050
0.010 0.065 0.020 0.010 0.197 0.157
E e H h L k ddd
6.20 0.50 1.27
0.228 0.010 0.016
0.244 0.020 0.050
0 (min.), 8 (max.) 0 .10 0.004
1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
Figure 12. External components placement example for DFN package
16/18
PM8834
Revision history
7
Revision history
Table 8.
Date 13-Oct-2008
Document revision history
Revision 1 Initial release. Changes
17/18
PM8834
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
18/18

▲Up To Search▲

Price & Availability of PM8834QTR

	To Download PM8834QTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .